Manager III, Software Development, Verification Team Lead
Annapurna Labs Ltd. · Tel Aviv, Israel · Software Development
Full-timeLead
About the role
Annapurna Labs is the team behind AWS Graviton the industry's most advanced ARM-based server SoC.
We operate like a start-up with the scale of the world's largest cloud provider.
We're looking for a Senior Design Verification Technical Lead- a design verification technical lead that is responsible for complex SoC sub-system, with cutting edge technology for Graviton server SoC.
• It starts at product definition- we engage from day one, shaping requirements and translating product intent into verification strategies before a single line of RTL is written
• It extends into software- we work side-by-side with SW teams, verifying hardware-software interfaces and ensuring seamless integration across the stack
• It reaches into physical design- we verify physical design aspects within functional verification, bridging the gap between logical correctness and silicon reality
• It closes the loop- from spec to silicon, our verification touches every team and every stage of chip development
What Sets Us Apart
Agentic AI is embedded in our workflow- not as an experiment, but as a core part of how we design and verify chips
Cutting edge methodologies drive every stage of our verification process
Relentless innovation- we don't settle; we actively seek new approaches that raise the bar on silicon quality
We do classic functional verification (SV/UVM/TLM), but beyond that, we touch physical design aspects, to ensure that the quality of our silicon is beyond logical functionality
Performance optimization at all levels is at the heart of our targets on top of logical correctness verification
Watch these videos to learn more about Annapurna Labs and the Graviton project.
AWS re:Invent 2025 - Keynote with Peter DeSantis and Dave Brown: https://www.youtube.com/watch?v=JeUpUK0nhC0
AWS re:Invent 2025 - AWS Graviton https://www.youtube.com/watch?v=haSHl2BLhm8
Key job responsibilities
What You'll Do
Develop and execute verification plans for IO sub-systems- covering interconnect
protocols, peripheral interfaces, and system-level integration
Verify IO sub-system features including interconnect protocols, various accelerators
engines
C embedded SW programing and SW debug skills
Build and maintain UVM-based verification environments for IO sub-systems
Verify ARM advanced interconnect protocols (AMBA CHI/ACE/AXI) ensuring correct coherency transactions, performance verification, and protocol compliance
Verify the IO virtualization SMMU/TLB operations, page table walks, translation
granules, and memory attributes (cache-ability, share-ability)
Develop constrained-random and directed test strategies targeting corner cases in IO protocol hazards, coherency races, and system boundary conditions
Drive coverage closure using functional coverage models, assertion-based verification,
and formal methods where applicable
Contribute to performance verification — ensuring micro-architectural
implementations meet performance targets alongside correctness
A day in the life
You start by reviewing operational metrics and system health dashboards, then connect with your engineers during stand-ups to unblock priorities and provide technical guidance. Midday, you might partner with product management to refine upcoming roadmap items or review a design document from a senior engineer on your team. You regularly hold one-on-ones focused on career growth and development planning. Throughout the day, you shift between strategic planning sessions, cross-team alignment discussions, and writing narratives that communicate your team's vision and progress to leadership.
- 8+ years of experience with full-chip/system-level verification of a large-scale SoC
- Experience with Test Writing and SW development (C/C++/Assembly)
- Hands-on verification/validation experience, including: debugging emulation and/or silicon platforms, waveform debugging, coverage definition and analysis, etc.
- Knowledge of the following programming languages: Perl/Bash/TCl/Python
- Knowledge of Processors, PCIe, Ethernet, DDR
- Knowledge of Hardware Verification concepts and tools (UVM , Coverage Driven verification), Verilog/SystemVerilog/Specman
Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner.
We operate like a start-up with the scale of the world's largest cloud provider.
We're looking for a Senior Design Verification Technical Lead- a design verification technical lead that is responsible for complex SoC sub-system, with cutting edge technology for Graviton server SoC.
• It starts at product definition- we engage from day one, shaping requirements and translating product intent into verification strategies before a single line of RTL is written
• It extends into software- we work side-by-side with SW teams, verifying hardware-software interfaces and ensuring seamless integration across the stack
• It reaches into physical design- we verify physical design aspects within functional verification, bridging the gap between logical correctness and silicon reality
• It closes the loop- from spec to silicon, our verification touches every team and every stage of chip development
What Sets Us Apart
Agentic AI is embedded in our workflow- not as an experiment, but as a core part of how we design and verify chips
Cutting edge methodologies drive every stage of our verification process
Relentless innovation- we don't settle; we actively seek new approaches that raise the bar on silicon quality
We do classic functional verification (SV/UVM/TLM), but beyond that, we touch physical design aspects, to ensure that the quality of our silicon is beyond logical functionality
Performance optimization at all levels is at the heart of our targets on top of logical correctness verification
Watch these videos to learn more about Annapurna Labs and the Graviton project.
AWS re:Invent 2025 - Keynote with Peter DeSantis and Dave Brown: https://www.youtube.com/watch?v=JeUpUK0nhC0
AWS re:Invent 2025 - AWS Graviton https://www.youtube.com/watch?v=haSHl2BLhm8
Key job responsibilities
What You'll Do
Develop and execute verification plans for IO sub-systems- covering interconnect
protocols, peripheral interfaces, and system-level integration
Verify IO sub-system features including interconnect protocols, various accelerators
engines
C embedded SW programing and SW debug skills
Build and maintain UVM-based verification environments for IO sub-systems
Verify ARM advanced interconnect protocols (AMBA CHI/ACE/AXI) ensuring correct coherency transactions, performance verification, and protocol compliance
Verify the IO virtualization SMMU/TLB operations, page table walks, translation
granules, and memory attributes (cache-ability, share-ability)
Develop constrained-random and directed test strategies targeting corner cases in IO protocol hazards, coherency races, and system boundary conditions
Drive coverage closure using functional coverage models, assertion-based verification,
and formal methods where applicable
Contribute to performance verification — ensuring micro-architectural
implementations meet performance targets alongside correctness
A day in the life
You start by reviewing operational metrics and system health dashboards, then connect with your engineers during stand-ups to unblock priorities and provide technical guidance. Midday, you might partner with product management to refine upcoming roadmap items or review a design document from a senior engineer on your team. You regularly hold one-on-ones focused on career growth and development planning. Throughout the day, you shift between strategic planning sessions, cross-team alignment discussions, and writing narratives that communicate your team's vision and progress to leadership.
Basic qualifications
- Electrical/Computer Science engineer- 8+ years of experience with full-chip/system-level verification of a large-scale SoC
- Experience with Test Writing and SW development (C/C++/Assembly)
- Hands-on verification/validation experience, including: debugging emulation and/or silicon platforms, waveform debugging, coverage definition and analysis, etc.
Preferred qualifications
- Knowledge of ARM architecture- Knowledge of the following programming languages: Perl/Bash/TCl/Python
- Knowledge of Processors, PCIe, Ethernet, DDR
- Knowledge of Hardware Verification concepts and tools (UVM , Coverage Driven verification), Verilog/SystemVerilog/Specman
Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner.